All-Digital Reconfigurable SRAM-Based Compute-in-Memory Macro for TinyML Devices

Watch a technical conference talk from tinyML Asia 2022 exploring an innovative all-digital reconfigurable SRAM-based compute-in-memory macro design for TinyML devices. Learn how this novel approach addresses key challenges in AI-to-device integration, including device heterogeneity and MCU constraints. Discover the development of a 10T multi-logic SRAM cell supporting multiple operation modes like writing, reading, and bit-wise logical calculations. Examine how the design implements pipelined schemes and concurrent reading capabilities to improve performance, while maintaining compatibility with standard top-down digital implementation flow. Follow along as the speaker presents detailed simulation results using Cadence Virtuoso with a 28nm process node, comparing the proposed solution against other state-of-the-art designs in the field of compute-in-memory architectures.