Enhancing Neural Processing Units with Digital In-Memory Computing

Watch a technical conference talk from the tinyML Summit 2023 exploring STMicroelectronics' development of an experimental low-power Neural Processing Unit (NPU) that integrates Digital In-Memory Computing (DIMC) SRAM with a modular dataflow inference engine. Learn how this 40nm architecture with DIMC-SRAM tiles performs in-memory binary computations to increase computational efficiency of binary layers, achieving up to 40x higher TOPS/W efficiency compared to traditional implementations. Discover how the ST Neural compilation toolchain automatically maps binary and mixed-precision Neural Networks on the NPU, with insights into its real-world application in Face Presence Detection, demonstrating 3ms latency and peak efficiency of 100 TOPS/W for binary in-memory computations. Presented by Danilo PAU, Technical Director, IEEE and ST Fellow at STMicroelectronics, this 12-minute talk delves into overcoming Von Neumann architecture limitations through novel computational memory designs for edge computing applications.