Benchmarking and Modeling of Analog and Digital SRAM In-Memory Computing Architectures

Explore a 15-minute research symposium presentation that delves into the comparison and benchmarking of analog and digital SRAM in-memory computing architectures for deep neural network accelerators. Learn about the emerging hardware paradigm of in-memory-computing and its role in breaking the memory wall while enabling massive computational parallelism. Discover the distinctions between analog in-memory-computing (AIMC) and digital in-memory-computing (DIMC) approaches, examining their respective trade-offs in accuracy, efficiency, and dataflow flexibility. Follow along as PhD student Pouya Houshmand from KU Leuven presents an analytical cost model for energy and throughput, reviews published architectures, and demonstrates workload scheduling across various IMC architectures for comprehensive network efficiency analysis, providing valuable insights into workload-hardware co-design strategies.