Hardware Description Languages (HDL) Courses and Certifications

Build a Modern Computer from First Principles: From Nand to Tetris (Project-Centered Course)

27 ratings

Build a working 16-bit computer from first principles: specify logic gates in HDL, construct an ALU and RAM chips, then write Hack machine-language programs and an assembler.

• Coursera
• 8 weeks, 5 hours a week
• Self-Paced
• Paid Course

• Best of All Time

Hardware Description Languages for FPGA Design

632 ratings at Coursera

Design logic in VHDL and Verilog: code comparators, flip-flops, counters, memories and state machines, then verify them with test benches in ModelSim simulation.

• Coursera
• 4 weeks, 9 hours a week
• Self-Paced
• Paid Course

NPTEL;  IIT Bombay

Electronics - Advanced VLSI Design

30 ratings

Explore advanced CMOS VLSI design, from logical effort and low-power circuits to hardware description languages, automation, testing, and verification.

• YouTube
• 1 day 20 hours
• Self-Paced
• Free Video

Introducción al diseño de hardware con Verilog

49 ratings

Aprende el lenguaje de descripción de hardware Verilog, utilizado en la industria en el diseño de hardware digital y microprocesadores a la medida.

• edX
• 5 weeks, 6-8 hours a week
• Self-Paced
• Free Online Course (Audit)

Career Certificate

FPGA Design for Embedded Systems

1751 ratings at Coursera

Design FPGA and CPLD systems: write Verilog and VHDL RTL, run synthesize-simulate-program-debug tool flows, and integrate soft-core processors and third-party IP on evaluation boards.

• Coursera
• 8 weeks, 10 hours a week
• Self-Paced
• Paid Course
• 4 courses

SOC Verification using SystemVerilog

6532 ratings at Udemy

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language

• Udemy
• 4 hours 15 minutes
• Self-Paced
• Free Online Course

Verification Series Part 1: SystemVerilog Essentials

4314 ratings at Udemy

Learn SystemVerilog for RTL verification: build layered testbenches with generator, driver, monitor and scoreboard classes, constrained random stimulus, queues, dynamic arrays and interprocess communication.

• Udemy
• 14 hours 17 minutes
• Self-Paced
• Paid Course

Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

3971 ratings at Udemy

From an expert with 15+ years experience. Core Design principles for VLSI, Soc, Processor and FPGA. VHDL alternative.

• Udemy
• 12 hours 41 minutes
• Self-Paced
• Paid Course

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

2024 ratings at Udemy

Learn Verilog modeling styles, synthesizable FSMs, memories and testbenches while building FPGA projects such as UART, PWM and DAC interfaces in Xilinx Vivado.

• Udemy
• 16 hours 37 minutes
• Self-Paced
• Paid Course

Verification Series Part 3: UVM Essentials

1846 ratings at Udemy

Build UVM verification environments from scratch: reporting macros, uvm_object and uvm_component, config_db, phases, TLM, and sequences, verifying combinational and sequential adders.

• Udemy
• 10 hours 52 minutes
• Self-Paced
• Paid Course

Verilog HDL Fundamentals for Digital Design and Verification

1832 ratings at Udemy

Build a strong Verilog language foundation by implementing combinational / sequential digital circuits and testbenches

• Udemy
• 5 hours 23 minutes
• Self-Paced
• Paid Course

Learn SystemVerilog Assertions and Coverage Coding in-depth

1772 ratings at Udemy

Become skilled in two key aspects of SystemVerilog used to ensure quality and completeness in all Verification jobs.

• Udemy
• 4 hours 50 minutes
• Self-Paced
• Free Online Course

Introduction to VHDL for FPGA and ASIC design

1519 ratings at Udemy

From VHDL basics to sophisticated testbench coding

• Udemy
• 9 hours 19 minutes
• Self-Paced
• Paid Course

Coursera

SystemVerilog Tutorials: Hardware Design & Verification

Design RTL in SystemVerilog: write parameterized modules, use typedef, enum and struct, model combinational and sequential logic, and build a simulated modular calculator with state machine.

• Coursera
• 3 weeks, 2 hours a week
• Self-Paced
• Paid Course

Hackaday

Learning Verilog for FPGAs - The Tools and Building an Adder

7 ratings

Model, simulate, and verify a two-bit combinational adder in Verilog using EDA Playground before synthesizing it for an FPGA.

• YouTube
• 19 minutes
• Self-Paced
• Free Video