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Learn about Xsight Labs' X-Series Ethernet switch architecture designed for AI infrastructure through this 18-minute conference presentation. Discover how the X-Series differentiates itself with a truly software-defined programmable architecture featuring 3072 Harvard architecture cores operating on a run-to-complete model, providing superior flexibility compared to competitors' fixed pipelines. Explore the switch's capabilities for parallel packet operations, recursion, and extensive header processing including 11 layers of MPLS and various encapsulations. Understand how this design optimizes performance for emerging AI-centric protocols such as Ultra Ethernet (UEC) and ESON, enabling customizable congestion management and efficient in-flight packet handling. Examine the technical specifications including 450 nanosecond latency performance, exceptional buffer utilization consistently above 86% under heavy load, and disruptive low power consumption under 200 watts for a 12.8T switch. Learn about the software-defined physical layer supporting diverse SERDES speeds from 10G to 200G with mixed-and-matched configurations for connecting new and legacy interfaces. Discover the programming model evolution from assembler-based with Python wrappers to customer-developed P4 compilers, and explore deployment scenarios for edge environments including half-rack to two-rack configurations, satellites, and base stations with significant reductions in power, rack space, and cost.
