Proximity is All You Need - Two Tricks for Chiplet Interconnects

This 12-minute conference talk from the Scalable Parallel Computing Lab (SPCL) at ETH Zurich addresses the growing challenges of optimizing chiplet interconnect topologies within technological and packaging constraints. Explore two innovative techniques developed under Patrick Iff's leadership that enhance chiplet interconnects while respecting distance limitations of various packaging technologies. Learn about key packaging constraints before diving into HexaMesh, an optimal tiling scheme that minimizes diameter and maximizes bandwidth across chiplet architectures. Discover how the brickwall arrangement enables six-neighbor connectivity, surpassing traditional four-neighbor topologies. See how Folded HexaTorus builds upon HexaMesh by using slightly longer links to achieve symmetry (vertex transitivity) while significantly reducing network diameter. Get introduced to RapidChiplet, a comprehensive toolchain for chiplet evaluation, simulation, and design space exploration that helps engineers analyze and optimize chiplet-based architectures efficiently. Gain insights into the future of chiplet interconnects and how these techniques are redefining the boundaries of scalable, high-bandwidth computing systems.