RapidChiplet - How to Explore the Design Space of Inter-Chiplet Interconnects

Explore the design space of inter-chiplet interconnects through this 12-minute conference presentation from ETH Zurich's Scalable Parallel Computing Lab. Learn why chiplet architectures are emerging as a solution to monolithic chip scaling challenges and discover the vast design space of inter-chiplet interconnects (ICI), including factors like chiplet number, size, placement, topology, bandwidth, and packaging technology. Understand how RapidChiplet, a fast latency and throughput prediction toolchain, addresses the speed limitations of traditional ICI simulators by trading minimal accuracy (0.25%–30.15%) for dramatic speedup improvements (427x–137,682x faster than cycle-level simulations). Examine the toolchain's latency and throughput proxy methods, evaluate its accuracy and performance benefits, and see how this approach enables rapid exploration of hundreds of thousands of design points for optimization algorithms and machine learning models. The presentation covers the motivation behind chiplet technology, the complexity of ICI design decisions, RapidChiplet's architectural overview, its prediction methodologies, comprehensive evaluation results, and practical applications for chiplet architecture design space exploration.