NY State-Licensed Certificates in Design, Coding & AI — Online
Learn EDR Internals: Research & Development From The Masters
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Learn about the essential tasks in the VLSI design process through this lecture covering global placement, legalization, detailed placement, and post-placement optimizations. Explore analytical placement methods, timing-driven placement techniques, scan chain reordering strategies, and spare cell placement approaches that optimize chip performance and manufacturability.
Syllabus
Placement
Taught by
NPTEL-NOC IITM