VLSI Courses and Certifications

NPTEL;  IIT Bombay

Electronics - Advanced VLSI Design

30 ratings

Explore advanced CMOS VLSI design, from logical effort and low-power circuits to hardware description languages, automation, testing, and verification.

• YouTube
• 1 day 20 hours
• Self-Paced
• Free Video

VLSI CAD Part I: Logic

557 ratings at Coursera

Learn how chip design tools work inside: computational Boolean algebra, BDDs and SAT, two-level and multi-level logic synthesis, factor extraction, and don't-care optimization.

• Coursera
• 6 weeks, 4 hours a week
• Self-Paced
• Paid Course

CMOS Analog VLSI Design

59 ratings

This course deals with the basic theory of analog circuits, design principles and techniques for analog ICs blocks implemented in CMOS Technology.

• YouTube
• 1 day 7 hours
• Self-Paced
• Free Video

VLSI CAD Part II: Layout

284 ratings at Coursera

Learn how VLSI CAD tools work: technology mapping by recursive tree covering, iterative and analytic ASIC placement, maze routing, and static timing analysis with ATs, RATs, and slacks.

• Coursera
• 6 weeks, 4 hours a week
• Self-Paced
• Paid Course

NPTEL;  IIT Kharagpur

Digital VLSI Testing

8 ratings

In this context, the course attempts to expose the students and practitioners to the most recent, yet fundamental, VLSI test principles and DFT architectures in an effort to help them design better quality products that can be reliably manufactured in la…

• YouTube
• 1 day 3 hours
• Self-Paced
• Free Video

L&T EduTech Career Certificate

Chip based VLSI design for Industrial Applications

204 ratings at Coursera

Design digital and VLSI circuits: apply Boolean algebra and state machines, simulate CMOS chips in Electric VLSI, program VHDL in Xilinx ISE, and build FPGA systems in Vivado.

• Coursera
• 8 weeks, 10 hours a week
• Self-Paced
• Paid Course
• 4 courses

L&T EduTech

VLSI Chip Design and Simulation with Electric VLSI EDA Tool

44 ratings at Coursera

Design and simulate CMOS chips in the Electric VLSI EDA tool: MOS transistors, stick diagrams, inverters, amplifiers, logic gates and half adders with DRC, ERC and LTspice.

• Coursera
• 3 weeks, 5 hours a week
• Self-Paced
• Paid Course

VLSI - Essential concepts and detailed interview guide

1188 ratings at Udemy

Revise VLSI physical design end to end: floorplanning, placement, clock tree synthesis, static timing analysis with real clocks, crosstalk and glitch analysis, routing DRC, parasitic extraction.

• Udemy
• 11 hours 21 minutes
• Self-Paced
• Paid Course

Complete ASIC Design Flow: VLSI From Idea to Silicon

123 ratings at Udemy

Full Digital IC Design Flow: Verilog, Synthesis, DFT, CDC, Low‑Power, & PnR with Cadence & Synopsys USE PROMO JUST-13

• Udemy
• 46 hours
• Self-Paced
• Paid Course

IIT Guwahati;  NPTEL

C-Based VLSI Design

1 rating

Learn how high-level synthesis translates C code into RTL hardware and how coding and compiler optimizations improve circuit performance.

• Swayam
• 12 weeks
• Available until Oct 9, 2026
• Free Online Course

VLSI DFT Basics: From Industry Perspective

105 ratings at Udemy

The purpose of DFT testing in VLSI along with industry standard DFT implementation flows

• Udemy
• 3 hours
• Self-Paced
• Paid Course

IIIT-Delhi;  NPTEL

VLSI Design Flow: RTL to GDS

Covers the complete RTL-to-GDS VLSI workflow, from Verilog modeling and logic synthesis through physical design, testing, routing, and sign-off.

• Swayam
• 12 weeks
• Available until Oct 9, 2026
• Free Online Course

NPTEL;  IIT Madras

VLSI Data Conversion Circuits

1 rating

Analyze and design CMOS ADCs and DACs, from sampling and quantization fundamentals through delta-sigma modulators, flash ADCs, and current-steering DACs.

• YouTube
• 2 days 6 hours
• Self-Paced
• Free Video

NPTEL-NOC IITM

Placement in VLSI Design - Global, Legalization, and Detailed Placement

An overview of VLSI placement workflows, from global and detailed placement through legalization and post-placement optimization.

• YouTube
• 43 minutes
• Self-Paced
• Free Video

Learn to build OVM & UVM Testbenches from scratch

3221 ratings at Udemy

Learn and Start building Verification Testbenches in SystemVerilog based Verification Methodologies - OVM and UVM

• Udemy
• 5 hours 28 minutes
• Self-Paced
• Free Online Course