Static Timing Analysis Courses and Certifications

NPTEL-NOC IITM

Static Timing Analysis - I: Basic Concepts and Constraints in VLSI Design Flow

Discover the basic concepts of static timing analysis in VLSI design, including zero/double clocking problems, constraints, and modeling using arrival and required time.

• YouTube
• 53 minutes
• On-Demand
• Free Video

NPTEL-NOC IITM

Static Timing Analysis - Part 2: Hold Time Failure and Transparent Latch Design

Analyze hold time failures and maximum delay constraints for flipflop and transparent latch designs in computational datapath subsystems.

• YouTube
• 34 minutes
• On-Demand
• Free Video

NPTEL-NOC IITM

Static Timing Analysis for CMOS Latch and Flipflop Designs - Lecture 11.1

Learn static timing analysis for CMOS latch and flipflop designs, including setup and hold time characterization and maximum delay constraints for combinational subsystems.

• YouTube
• 32 minutes
• On-Demand
• Free Video

ASIC Synthesis-STA-Physical Design(PD):Cadence+Synopsys flow

492 ratings at Udemy

ASIC flow, Synthesis, STA, Physical Design - Cadence Genus, Tempus, Innovus tool flow & Synopsys ICC2 tool flow

• Udemy
• 1 day 16 hours 50 minutes
• On-Demand
• Paid Course

VSD - Static Timing Analysis - I

2789 ratings at Udemy

Learn essential VLSI static timing analysis checks for design closure. Gain practical insights into industry-standard STA practices, from basic concepts to advanced techniques for quality analysis.

• Udemy
• 3 hours 29 minutes
• On-Demand
• Paid Course

VSD - Static Timing Analysis - II

772 ratings at Udemy

Explore full chip static timing analysis using OpenTimer, an open-source EDA tool. Apply concepts like PBA and CPPR to analyze complex designs such as USB controllers and DDR interfaces.

• Udemy
• 4 hours 2 minutes
• On-Demand
• Paid Course

Fundamental of Static Timing Analysis (Part 1)

131 ratings at Udemy

Master fundamental concepts of Static Timing Analysis, including timing arcs, delay calculations, liberty files, and ASIC design stages for effective RTL to GDS implementation.

• Udemy
• 4 hours 59 minutes
• On-Demand
• Paid Course

FPGA Timings P1:Static Timing Analysis(STA) with Vivado 2024

47 ratings at Udemy

Discover FPGA timing analysis fundamentals using Vivado 2024, covering setup/hold constraints, slack calculations, and XDC timing constraints for reliable digital designs.

• Udemy
• 4 hours 48 minutes
• On-Demand
• Paid Course

NPTEL-NOC IITM

Static Timing Analysis: Minimum Delay Constraint for Transparent Latches - Part 2.1

Establish minimum delay constraints for transparent latch designs in computational datapath subsystems, addressing hold time failures and contamination delays.

• YouTube
• 10 minutes
• On-Demand
• Free Video

NPTEL-NOC IITM

Static Timing Analysis II - Mechanics, Timing Paths, and Slack Computation

Delve into the mechanics of static timing analysis (STA), including timing paths, graphs, delay calculations, and slack computation for better design analysis.

• YouTube
• 1 hour 14 minutes
• On-Demand
• Free Video

NPTEL-NOC IITM

Technology Library and Constraints in Delay Calculation and Static Timing Analysis

Understand the impact of technology library and constraints on delay calculation and static timing analysis.

• YouTube
• 18 minutes
• On-Demand
• Free Video

NPTEL-NOC IITM

Static Timing Analysis using OpenSTA

Discover how to install and use OpenSTA, an open-source static timing analysis tool, in this concise tutorial.

• YouTube
• 14 minutes
• On-Demand
• Free Video

集成电路设计与EDA

掌握基于标准单元的大规模数字集成电路设计方法，学习Verilog HDL可综合电路设计、主流EDA工具使用及Linux平台操作，培养完整的数字IC设计能力。

• XuetangX
• On-Demand
• Free Online Course

Digital Timing Basics for VLSI Interview & SoC Design

898 ratings at Udemy

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design

• Udemy
• 4 hours 1 minute
• On-Demand
• Paid Course

Mastering Digital VLSI, ASIC and Verilog Interview Questions

400 ratings at Udemy

SOC, VLSI, ASIC Design, AI Hardware Design, STA, HDL, Digital Design, Clock Domain Crossing, Low Power Design

• Udemy
• 4 hours 33 minutes
• On-Demand
• Paid Course