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This course provides a comprehensive overview of key concepts in VLSI SoC Design and various techniques involved in the VLSI design flow. The course provides a comparison between ASIC and FPGA technologies and focuses on advanced digital design and Verilog HDL, and also on various design styles, different techniques involved for partitioning, floor-planning, routing, etc, and also gives an insight into various timing procedures and timing closure.
Intended audience
ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, Physical Design Engineer, Physical Verification Engineer, STA Engineer, Layout Design Engineer, VLSI Physical Design Engineer
Prerequisites
- Prior knowledge in Digital electronics and Verilog HDL - Competency Level - Basic to Intermediate
Assessment & certification
- Assessment fee: Included — no extra fee
- Assessment mode: Online
- Assessment type: MCQ
- Assessment provider: Maven Silicon
- Certificate provider: SWAYAM Plus and Maven Silicon
NCrF level: 7 (NCrF credit-eligible)
