This course aims to provide a comprehensive journey into mastering verification methodologies in VLSI design by covering a range of modules, from RTL design to Verification concepts. It introduces the basics and then discusses in depth SystemVerilog language concepts, memories, interfaces, object-oriented programming, randomization, functional coverage, and more. The course offers an overview of the Universal Verification Methodology.
Intended audience
ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, Verification Engineer, ASIC Verification Engineer, SoC Verification Engineer, Design Verification Engineer, VLSI Verification Engineer
Prerequisites
- Prior knowledge in Digital electronics and Verilog HDL, Competency level - Intermediate
Assessment & certification
- Assessment fee: Included — no extra fee
- Assessment mode: Online
- Assessment type: MCQ
- Assessment provider: Maven Silicon
- Certificate provider: SWAYAM Plus and Maven Silicon
NCrF level: 7 (NCrF credit-eligible)