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VLSI Verification - Campus Connect

via SWAYAM Plus

Overview

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This course aims to provide a comprehensive journey into mastering verification methodologies in VLSI design by covering a range of modules, from RTL design to Verification concepts. It introduces the basics and then discusses in depth SystemVerilog language concepts, memories, interfaces, object-oriented programming, randomization, functional coverage, and more. The course offers an overview of the Universal Verification Methodology.

Intended audience

ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, Verification Engineer, ASIC Verification Engineer, SoC Verification Engineer, Design Verification Engineer, VLSI Verification Engineer

Prerequisites

  • Prior knowledge in Digital electronics and Verilog HDL, Competency level - Intermediate

Assessment & certification

  • Assessment fee: Included — no extra fee
  • Assessment mode: Online
  • Assessment type: MCQ
  • Assessment provider: Maven Silicon
  • Certificate provider: SWAYAM Plus and Maven Silicon

NCrF level: 7 (NCrF credit-eligible)

Syllabus

  • Week 1: Introduction to VLSI Design
  • Week 2: SoC ASIC Design Flow
  • Week 3: Advanced Digital Design
  • Week 4: Digital Design Hands-On
  • Week 5: Static Timing Analysis
  • Week 6: Verilog HDL
  • Week 7: Verilog HDL Hands On
  • Week 8: SystemVerilog HDVL
  • Week 9: SystemVerilog Assertions
  • Week 10: Universal Verification Methodology
  • Week 11: Business Communication
  • Week 12: Assessments

Taught by

Maven Silicon Experts

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