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Explore micro-architectural security vulnerabilities and defense mechanisms in this conference session from CHES 2025, chaired by Thomas Eisenbarth. Delve into the latest research on hardware-level security threats that exploit processor design features, examining how attackers can leverage micro-architectural components like caches, branch predictors, and speculative execution units to extract sensitive information. Learn about cutting-edge attack vectors, side-channel analysis techniques, and countermeasures being developed to protect against these sophisticated threats. Gain insights from leading researchers in the field as they present their findings on micro-architectural security challenges facing modern computing systems, with detailed papers and presentation materials available through the CHES 2025 program.
