Building an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre-Silicon Correlation

Explore a comprehensive framework for building an interoperable chiplet ecosystem through golden die validation methodology in this 21-minute conference presentation. Learn how the UCIe standard serves as the foundation for validating chiplet interoperability as AI, cloud, and HPC applications drive demand for disaggregated architectures. Discover how existing UCIe IP can function as a reference golden die in the absence of open-source alternatives, utilizing BIST and RAS features calibrated against known signals to verify link integrity. Understand the detailed workflow for characterizing TX, interconnect, and RX components using calibrated test points and stress conditions, with results correlated to pre-silicon EDA simulations. Examine compliance testing approaches that support scalable, multi-vendor integration and explore pathways for compliance with beyond-224G connectivity leveraging D2D links. Gain insights into how this methodology accelerates design cycles, enhances system reliability, and contributes to establishing an open chiplet economy through robust interoperability validation.