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Explore a 40-minute conference talk from the DPDK Project where Lukáš Kekely of DynaNIC discusses how RTE Flow groups can be specialized for FPGA SmartNICs. Learn about the growing importance of RTE Flow API for offloading packet processing to SmartNICs, and understand the fundamental trade-off between universal support and performance. Discover why DPU-based SmartNICs offer generic RTE Flow support at the cost of performance—a critical issue when processing short packets at 400G wirespeed. The presentation explains how FPGA SmartNICs provide an alternative approach, delivering wirespeed performance despite resource limitations by implementing application-specific processing pipelines with match-action tables optimized for specific use cases. These tables can be represented as RTE Flow groups, enabling straightforward software control. Gain detailed insights into this specialized approach and its key advantages for high-performance network processing.
