Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow

Learn about monitoring 400G network traffic through this technical presentation that explores DPDK implementation with FPGA-based SmartNIC and RTE Flow. Discover how CESNET developers created the first 400G FPGA-based SmartNIC supporting DPDK, utilizing Intel Agilex 7 FPGA for hardware acceleration. Explore the challenges of monitoring packets at 400G wire speeds and understand how the processing pipeline implements packet marking, filtering, and other capabilities at 400 Gbps. Gain insights into configuring RTE flow for accelerated monitoring and various network processing tasks, addressing the growing demands of high-speed network traffic monitoring.