SwCC - Software-Programmable and Per-Packet Congestion Control in RDMA Engine

Learn about SwCC, a novel RDMA engine design that enables software-programmable and per-packet congestion control through on-NIC RISC-V cores in this 19-minute conference presentation from USENIX ATC '25. Discover how researchers from Zhejiang University address the limitations of hardwired congestion control algorithms (CCAs) in current RDMA NICs, which struggle to adapt to rapidly evolving data center applications and increasingly bursty ML workloads at higher network speeds of 400-800 Gbps. Explore the technical architecture of SwCC, including its carefully designed RISC-V core memory subsystem, engine architecture, and optimized interaction mechanisms between RISC-V cores and other NIC resources to prevent performance degradation. Examine the comprehensive software API framework that enables developers to deploy new CCAs with minimal engineering effort, supporting implementation of rate-based, window-based, and credit-based congestion control algorithms using C language. Review experimental results from the Xilinx U280 FPGA prototype demonstrating that SwCC achieves performance comparable to commercial RDMA NICs like Mellanox ConnectX-5, with both systems reaching 3.1 µs control loop RTT and requiring 512B packet size to achieve line-rate traffic at 100 Gbps, while providing significantly enhanced flexibility for congestion control customization and scalability to higher network bandwidths in potential ASIC implementations.