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Watch a technical research symposium presentation exploring memory-oriented design strategies for Edge-AI hardware in XR applications. Delve into an investigation of hand detection and eye segmentation workloads, examining how deep neural networks perform under various quantization levels and hardware constraints. Learn about comparative analyses between CPU and systolic inference accelerator implementations across different technology nodes, with special focus on emerging non-volatile memory technologies like STT/SOT/VGSOT MRAM. Discover how integrating non-volatile memory into XR-AI inference pipelines can achieve significant energy benefits of 24% or more for specific inference rates, while also reducing area requirements by 30% or greater compared to traditional SRAM solutions. Follow along through key topics including methodology, workload analysis, quantization effects, benchmarking processes, CMOS workflow considerations, and performance metrics like inference per second (IPS) and crossover points.
