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Watch a 25-minute conference presentation from POPL 2018 exploring the integration of transactions into hardware relaxed memory architectures. Discover a general architectural framework that introduces transactions into various memory models including SC, TSO, ARMv8, and PPC. Learn how this framework incorporates flexible transaction aborts and execution capabilities previously limited to software transactional memory, while accounting for relaxed memory's characteristics as a distributed system without global time. Understand the abstraction theorems that demonstrate how the programmer API aligns with transactional expectations and intuitions. Presented by researchers Brijesh Dongol from Brunel University London, along with Radha Jagadeesan and James Riely from DePaul University, this talk provides valuable insights into the ongoing industrial and academic research in hardware transactional memory systems.
