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Learn about P4RTC, a groundbreaking approach that applies P4 programming language to run-to-completion (RTC) chip architecture in this 15-minute conference presentation from NSDI '25. Discover how researchers from Nanjing University and Huawei addressed the limitations of P4 programmable data planes by introducing a new P4 architecture model specifically designed for RTC chips with 1.2 Tbps bandwidth. Explore the comprehensive consolidation of experiences in applying P4 language to RTC architecture, including beneficial extern constructs that fully leverage RTC programmability capabilities. Gain insights into compiler design and implementation challenges, understand the performance model developed for profiling P4RTC performance on user-customized P4 code, and examine case-oriented evaluation results demonstrating enhanced P4 programmability and reduced RTC development burdens. Understand how this work addresses the cessation of next-generation Tofino chips and limited programmability issues in current P4 implementations, while learning about the practical applications and optimization strategies for P4RTC programs in high-performance networking environments.
