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Learn how to rapidly implement and test RISC-V extensions in QEMU through automated frontend generation techniques in this 26-minute conference talk from KVM Forum. Discover a comprehensive methodology for developing Qualcomm's qc_iu set of RISC-V extensions without requiring a compiler toolchain, starting with C++ code generation and progressing to LLVM IR production from instruction definitions provided by riscv-unified-db. Explore the application of the LLVM-based helper-to-tcg tool to generate TCG implementations for 143 out of 172 instructions, enabling an emulator-in-the-loop process ideal for rapid prototyping, validation, and design space exploration. Master automatic test generation techniques using the LLVM IR-based symbolic execution engine KLEE to create comprehensive per-instruction tests covering memory operations, branches, and corner cases, resulting in 289 tests across 143 instructions for each ISA specification version. Understand how this automated approach proves invaluable for identifying bugs in original instruction definitions and significantly reduces the entry cost and error-prone nature of adding support for new targets in QEMU. Gain insights into the evolution of the helper-to-tcg tool since its successful application to the Hexagon frontend, now enhanced for more general settings and broader applicability in architecture development workflows.
