VLSI - Verilog HDL - Handson

The course is designed to offer a refreshing approach to Verilog HDL, focusing on key concepts through a variety of RTL coding examples. It includes a hands-on project to help develop and strengthen the skills essential for effective RTL design.

Intended audience

ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, VLSI Design Engineer

Prerequisites

Prior knowledge in Digital electronics, Verilog HDL Competency Level - Basic to Intermediate

Assessment & certification

Assessment fee: Included — no extra fee
Assessment mode: Online
Assessment type: MCQ
Assessment provider: Maven Silicon
Certificate provider: SWAYAM Plus and Maven Silicon

Syllabus

Week 1: Verilog HDL Summary
Week 2: Verilog RTL Coding Examples
Week 3: Verilog Project

Taught by

Maven Silicon Experts

Reviews

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Intended audience

Prerequisites

Assessment & certification

Taught by

NY State-Licensed Certificates in Design, Coding & AI — Online

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