VLSI SoC Design using Verilog HDL

This course provides a concise yet comprehensive overview of key concepts in VLSI SoC Design, making it an ideal resource for those seeking insights into the intricate world of System-On-Chip design. The course provides an exploration of SoC design, a comparison between ASIC and FPGA technologies, and an in-depth look at the VLSI design flow. The course elevates your understanding in Verilog data types, operators, system tasks & functions, and engage in hands-on Verilog Labs.

Intended audience

ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, VLSI Engineer

Prerequisites

Prior knowledge in Digital electronics Competency Level - Basic to Intermediate

Assessment & certification

Assessment fee: Included — no extra fee
Assessment mode: Online
Assessment type: MCQ
Assessment provider: Maven Silicon
Certificate provider: ASIC Design Engineer, Design Engineer, FPGA Design Engineer, SoC Design Engineer, RTL Design Engineer, VLSI Engineer

Syllabus

Week 1: VLSI SoC Design
Week 2: Verilog HDL
Week 3: Verilog Reference Material
Week 4: Basic Verilog Labs
Week 5: Assessments

Taught by

Maven Silicon Experts

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Prerequisites

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