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VLSI - Verification Methodology Overview

via SWAYAM Plus

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Overview

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This course provides an understanding to the key concepts in the world of hardware verification. This course is designed to provide a comprehensive overview of verification methodologies, covering the verification process, reusable testbenches, verification environment architecture and constraint random coverage-driven verification.

Intended audience

Verification Engineer, ASIC Verification Engineer, FPGA Verification Engineer, Design Verification Engineer, SoC Verification Engineer

Prerequisites

  • Prior knowledge in Verilog HDL

Assessment & certification

  • Assessment fee: Included — no extra fee
  • Assessment mode: Online
  • Assessment provider: Maven Silicon
  • Certificate provider: SWAYAM Plus and Maven Silicon

Syllabus

  • Week 1: Introduction to Verification Methodology
  • Week 2: Verification Process
  • Week 3: Resuable TB
  • Week 4: Verification Environment Architecture
  • Week 5: Constraint Random Coverage Driven verification ( CRCDV)
  • Week 6: Assessments

Taught by

Sivakumar P R, Founder & CEO

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