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This course aims in providing a comprehensive journey into mastering verification methodologies in VLSI design by covering a range of modules, from introducing the basics to in-depth discussions on SystemVerilog language concepts, memories, interfaces, object-oriented programming, randomization, functional coverage, and more. The course offers case studies involving Dual Port RAM and Maven SoC using SystemVerilog testbenches and an overview of the Universal Verification Methodology.
Intended audience
Verification Engineer, ASIC Verification Engineer, SoC Verification Engineer, Design Verification Engineer, VLSI Verification Engineer
Prerequisites
- Prior knowledge in Digital electronics and Verilog HDL Competency level - Intermediate
Assessment & certification
- Assessment fee: Included — no extra fee
- Assessment mode: Online
- Assessment type: MCQ
- Assessment provider: Maven Silicon
- Certificate provider: SWAYAM Plus and Maven Silicon
NCrF level: 7 (NCrF credit-eligible)
