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The course provides an exploration to RISC-V RV32I RTL - Processor IP Verification using UVM, by delving into RISC-V architecture. The course begins with the Instruction Set Architecture, RV32I processor with a 5-stage pipeline continues with Linux OS fundamentals and transition to UVM, covering its architecture, stimulus modeling, phases, configuration etc.. The course engage with a hands-on labs for UVM setup, sequence creation, and register abstraction model.
Intended audience
Processor Architect, Processor Verification Engineer, RISC-V Verification Engineer, CPU Verification Engineer, VLSI Design Engineer, VLSI Verification Engineer
Prerequisites
- Prior knowledge in Digital electronics, Computer architecture, SystemVerilog HVL Competency level - Intermediate to Expert
Assessment & certification
- Assessment fee: Included — no extra fee
- Assessment mode: Online proctored
- Assessment type: MCQ
- Assessment provider: Maven Silicon
- Certificate provider: SWAYAM Plus and Maven Silicon
NCrF level: 7 (NCrF credit-eligible)
