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The course provides a holistic approach to the intricacies of RISC-V RV32I RTL - Processor IP Design using Verilog HDL aiming a solid foundation in RISC-V Instruction Set Architecture and progress through RTL architecture design, including a 5-stage pipelined implementation. The course also covers Verilog HDL, mastering data types, operators, and advanced techniques for verification with a hands-on labs and project to reinforce your skills and culminate in the creation of a multi-stage pipeline processor design using Verilog HDL.
Intended audience
Processor Architect, Processor Design Engineer, RISC-V Design Engineer, CPU Design Engineer, VLSI Design Engineer
Prerequisites
- Prior knowledge in Digital electronics, Computer architecture Competency level - Intermediate to Expert
Assessment & certification
- Assessment fee: Included — no extra fee
- Assessment mode: Online
- Assessment type: MCQ
- Assessment provider: Maven Silicon
- Certificate provider: Processor Architect, Processor Design Engineer, RISC-V Design Engineer, CPU Design Engineer, VLSI Design Engineer
NCrF level: 7 (NCrF credit-eligible)
