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This 17-minute conference talk by Mike Bartley, SVP VLSI at Tessolve, explores the testing challenges and solutions for Systems-in-Package (SiPs) based on chiplet technology. Learn how chiplets offer a new approach to building SiPs that improve yields and reduce costs by partitioning systems into discrete components connected via standardized interfaces. Understand the critical testing requirements for chiplet integration, as one defective die can cause entire package failure. Discover testing methodologies that enable individual chiplet re-testing within SiPs to meet performance, efficiency, power, size, cost, and quality challenges for automotive, 5/6G, VR, AI, and data center applications. This presentation builds on the "System In Package Testing" White Paper available on the Open Compute Project website and mentions ongoing work on version 2, with opportunities to join this initiative.
