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Learn about comprehensive test strategies for chiplet-based semiconductor systems in this 23-minute conference talk from the Open Compute Project. Explore the challenges and solutions for testing complex integrated systems that combine chiplets from multiple vendors, focusing on applications in HPC, data centers, automotive, and AI domains. Discover how chiplet-based integration offers advantages over monolithic designs including faster time-to-market and improved yields, while also presenting unique testing challenges for fault detection in final products. Examine key factors influencing chiplet-based design testing including multi-vendor chiplet integration, test coverage requirements from individual chiplets to product level, the importance of individual chiplet test data availability for system performance assurance, and substrate influence on overall system performance. Understand how these factors drive the need for System Level Test (SLT) implementation. Follow a detailed test strategy flow based on Known Good Die methodology designed to address these challenges while minimizing both test time and associated costs, providing practical insights for semiconductor professionals working with advanced packaging technologies.
