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The course focus on learning various DFT concepts like, the scan chain insertion, fault simulation, fault collapsing and structured techniques etc.. The course also focus on providing an exposure to tessent shell, which is an interface to tessent tools by a demo on Scan-chain insertion technique.
Intended audience
DFT Engineer, DFT Verification Engineer, DFT Architect, VLSI Design Engineer
Prerequisites
- Prior knowledge in Digital electronics, Verilog HDL Competency Level - Intermediate to Expert
Assessment & certification
- Assessment fee: Included — no extra fee
- Assessment mode: Online
- Assessment type: MCQ
- Assessment provider: Maven Silicon
- Certificate provider: DFT Engineer, DFT Verification Engineer, DFT Architect, VLSI Design Engineer
