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Explore CXL.mem memory expansion and sharing capabilities through packet-level simulation in this 42-minute conference talk. Learn how CXL.mem enables hosts to expand memory beyond individual servers using load and store instructions while facilitating memory sharing among endpoints through extended coherency management protocols. Discover the design and implementation of a comprehensive CXL.mem simulator built on SimPy, a Python-based discrete-event simulation framework, that models hosts, CXL switches, and endpoints. Master the simulator APIs to construct CXL topologies, define application control and data flows, and submit applications to specific hosts for execution while exploring new CXL switch architectures. Analyze the overheads of CXL coherency including access, serialization, snooping, and eviction delays, and examine how the simulator evaluates existing task schedulers and memory allocators. Gain simulation-driven insights to design CXL-aware task schedulers and optimize memory sharing performance in large-scale CXL.mem deployments, democratizing exploration of this emerging memory technology.
