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Explore the intricacies of estimating propagation and contamination delays in 3-Nand gates for various sizes in this 36-minute lecture. Delve into the concepts of effort delay and parasitic delay while focusing on characterizing the delay of NOR gates. Gain valuable insights into digital circuit analysis and performance optimization techniques presented by NPTEL-NOC IITM.
Syllabus
4.5 - Characterizing Delay of NOR gate
Taught by
NPTEL-NOC IITM