Stanford Seminar - Accelerating ML Recommendation with Over a Thousand RISC-V-Tensor Processors

This seminar examines the design of the ET-SoC-1, a 7nm system-on-chip with more than a thousand low-power RISC-V processors and distributed on-die memory. It covers the chip’s architecture, instruction set extensions, software, and benchmark performance for machine-learning recommendation workloads.

Syllabus

Introduction
The Chip
Challenges
Different approaches
Constraints
Energy Efficiency
Computing Neighborhood
Grouping
Parallelization
More Details
Memory System
Other Form Factors
Software
Vector Operations
Tensor Multiply
Example
Integer Operations
Instructions
Benchmarks
Maxion
Summary
Where are we
First silicon