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Explore innovative system-level architectures designed to overcome the critical memory and I/O bottlenecks that limit today's GenAI training and inference workloads in this 17-minute conference talk. Learn about groundbreaking solutions including custom HBM on FinFET base die technology that enables memory expansion and unprecedented bandwidth density while overcoming traditional HBM packaging constraints to break through the Memory Wall. Discover D2D-to-C2C fanout architectures that dramatically improve XPU-XPU and system-level interconnect bandwidth, power efficiency, and scalability, effectively addressing the I/O Wall and unlocking new possibilities for on-board and optical connectivity. Understand how these solutions create highly efficient, manufacturable GenAI systems built with open, scalable, chiplet-based architectures that align with Open Compute Project community goals and can enable orders of magnitude improvements in bandwidth, density, and flexibility for next-generation AI infrastructure.
