How to Fuzz an FPGA – My Experience Documenting Gowin FPGAs

This talk explains how to fuzz Gowin FPGAs to document their architecture and support open-source FPGA tools. It covers synthesis, routing, automation scripts, data extraction, limitations, and approaches for contributing to FOSS tool flows.

Syllabus

Intro
Welcome
Who am I
Outline
Logic tiles
Software
Synthesis
Get the license
Get the FPGA
Get the software
Read the manual
The synthesis tool
What is fuzzing
Step 1 Write a netlist
Step 2 Constraint file
Step 3 Tcl script
Python script
HP run
Binary trick
Balance balanced constant weight
Metaphasers
Routing
Other approaches
GDB example
Datafile example
Automated gdp scripts
Extracting the data
Speedup
Limitations
Clock Filter
Tile Format
Open Source FPGA
Project APIkura
Does Gowin provide a timing simulator