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Explore the hardware implementation challenges facing post-quantum cryptography in this 56-minute invited conference talk delivered at CHES 2025. Delve into the technical complexities and practical considerations involved in implementing quantum-resistant cryptographic algorithms in hardware systems. Learn about the current state of post-quantum cryptography hardware implementations, including performance bottlenecks, resource constraints, and optimization strategies. Discover the engineering challenges that arise when transitioning from classical cryptographic hardware to quantum-resistant alternatives, and examine potential solutions for efficient hardware deployment. Gain insights into the intersection of cryptographic theory and practical hardware design, with particular focus on the unique requirements and limitations that post-quantum algorithms impose on hardware implementations. Understand the implications for future cryptographic hardware development and the steps needed to prepare for the post-quantum era.
