Cache Side Channel Attacks - CPU Design As A Security Problem

This talk examines how the microarchitectural design of modern x86 CPUs enables cache side-channel attacks against private data across trust boundaries such as virtual machines and sandboxes. It covers attack methods, detection techniques using performance counters, and software mitigation challenges.

Syllabus

Intro
Cache Side Channel Attacks
Who am I
Scope
Why is this interesting
How the data cache works
Summary
How is memory stored
Example code
How it works
Cash attacks
Victim time
Prime and Probe
Flush Load
Eject In Time
Shared Memory
Side Channel Attacks
Detecting Side Channels
Performance Counters
Flush Reload
Detecting cache misses
Analyzing the original code
Is the form scan useless
Flush and flush
Detecting flush
Twostage detection
Problems
Mitigation
Questions