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Explore the challenges and innovative approaches in validating weak memory persistency models for Non-Volatile Memory (NVM) in this 21-minute conference talk from ACM SIGPLAN's FOWM'24. Delve into the limitations of traditional validation methods for memory consistency models when applied to NVM. Discover a proposed methodical memory hierarchy timing attack that utilizes instruction time-stamping to infer access destinations within the memory hierarchy, particularly focusing on Intel architectures. Learn about the complexities involved in interpreting timing information and how model learning techniques are employed to create a machine-readable representation of the target system. Gain insights into the automatic discernment of timing and ordering patterns of memory instructions through observations in a black-box fashion.
