Cooperation Between CPU and System Level Cache Using MPAM

Explore how Memory System Resource Partitioning and Monitoring (MPAM) enables cooperation between CPU and system-level cache in this Linux Plumbers Conference talk. Learn about MPAM's capability to provide fine-grained control over shared resources including CPU caches, memory bandwidth, and interconnect bandwidth within typical memory hierarchies that flow from CPU (L2/L3) through Network-on-Chip (NoC) to System Level Cache (SLC) and finally to DDR memory. Discover the challenges that arise when Memory System Controllers like SLC do not natively support MPAM's PartID tags, and examine proposed mechanisms that would enable SLC to leverage MPAM adjustments by allocating tasks based on these tags. Understand how this cooperation can lead to significant performance and energy efficiency improvements in modern computing systems.