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Explore how Broadcom's Tomahawk Ultra 51.2 terabit per second switch chip revolutionizes high-performance Ethernet networking for HPC and AI applications in this 39-minute conference presentation. Discover how this clean-slate design addresses traditional Ethernet limitations including high latency, small frame size constraints, packet overhead, and lossy networking to compete with InfiniBand in demanding computing environments. Learn about the chip's groundbreaking 250-nanosecond ball-to-ball latency, optimized packet-per-second processing for small message sizes, and support for in-network collectives (INC) that offload computation from XPUs during AI training. Examine advanced reliability features including link-layer retry (LLR) and credit-based flow control (CBFC) for lossless networking, along with topology-aware routing capabilities for complex HPC network optimization. Understand how the Tomahawk Ultra maintains pin compatibility with Tomahawk 5 for rapid OEM and ODM adoption while adhering to open Ethernet standards for compatibility and ease of management. Gain insights into Broadcom's Scale Up Ethernet (SUE) specification contribution to OCP and how this technology positions itself as an open, standards-based alternative to proprietary solutions like NVLink in scale-up architectures.
