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This session presents an advanced NIC simulation framework specifically designed for AI back-end environments. Learn about a new PCI NIC model that features bandwidth and latency modeling, credit-based flow control, RMA application emulation, and ML training load-based power consumption tracking. Discover how this open-sourced enhancement to an NS3-like network simulator provides developers with deep insights into complex data flows, helping identify performance bottlenecks and optimize throughput before hardware deployment. Explore how to incorporate PCIe RMA accelerator NIC elements into simulations, enabling more accurate testing and faster iteration cycles for next-generation AI/HPC training networks. Presented by Vijay Inavolu, Senior Principal Engineer at Marvell, this 22-minute talk from the Open Compute Project demonstrates how the framework can significantly reduce design costs and accelerate innovation in AI infrastructure development.
