Arm AMBA AXI Protocols Overview

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Coursera
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English
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5 hours 28 minutes
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Self-Paced
Level

Intermediate
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English

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Overview

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Introduction to AMBA® AXI is a practical introduction to the AXI (Advanced eXtensible Interface) protocol, a core building block of modern system-on-chip (SoC) designs. This course is designed for learners who want to strengthen their understanding of how data moves within complex computing systems. You’ll explore how AXI enables efficient, high-performance communication between processors, memory, and peripherals, and how protocol behaviour impacts system performance and correctness. Through short, focused videos and assessments, you’ll learn about AXI channels, transactions, ordering rules, atomic accesses, and key protocol features used in real-world designs. The course also includes coverage of recent AXI updates to ensure relevance to current platforms. By the end of the course, you’ll be able to read and reason about AXI transactions with confidence, making this knowledge directly applicable when working with hardware platforms, low-level software, or system architecture documentation.

Syllabus

Welcome

Welcome to Introduction to AMBA® AXI. This short video will walk you through how the course is structured, what you’ll learn, and how to approach the material. Take a moment to get oriented, then move on when you’re ready — the course is designed to let you learn at your own pace.

Introduction to AMBA AXI

In this module, you will build the foundational understanding needed for working with AMBA AXI. You’ll explore what the AMBA architecture is, why it was created, and how it has evolved to support increasingly complex system-on-chip designs. You’ll also be introduced to the AXI protocol - its purpose, its key features, and the role it plays within the broader AMBA family. By the end of the module, you’ll have a clear picture of how AMBA standardises on-chip communication and why AXI has become the most widely adopted protocol for high-performance, low-latency systems.

Channel Transfers and Transactions

This module introduces how information moves through the AXI protocol by exploring the structure and behaviour of channel-based communication. Learners will examine how the VALID/READY handshake enables flexible data flow, and how individual transfers combine to form complete read and write transactions. Through examples of single-data and multi-data transactions, the module illustrates how AXI separates responsibilities across channels to maintain efficiency. The module concludes by showing how AXI supports multiple active transactions, enabling high throughput in modern SoC designs.

Channel Signals in Detail

In this chapter, you’ll take a closer look at the signals that make AXI communication work. Each AXI channel uses a specific set of signals to coordinate intent, control data movement, manage access permissions, and report results. By understanding what these signals mean and how they interact, you’ll build a clearer picture of how AXI enables reliable, high-performance communication across a system. We’ll explore the purpose of key control and data signals, how channel dependencies influence system behaviour, and how features such as burst configuration, protection levels, caching hints, atomic access support, and Quality of Service build flexibility into the protocol. By the end, you’ll be able to recognise the role of these signals in shaping AXI transactions and appreciate why they matter when integrating components or analysing system performance.

Atomic Accesses

Welcome to this module on Atomic Accesses in the AXI protocol. In modern systems, multiple agents often need to access shared resources at the same time. In these situations, it’s not enough for transactions to be fast — they also need to be atomic, ensuring that critical read-modify-write sequences complete without interference. In this module, we’ll explore what atomic accesses are and why they are used. We’ll then look in detail at the two mechanisms AXI provides to support atomicity: locked accesses and exclusive accesses. You’ll see how each approach works, how they differ, and the trade-offs involved in their use. In particular, we’ll focus on how locked and exclusive accesses affect interconnect behaviour and bandwidth utilisation, and why exclusive accesses are generally preferred in high-performance systems. By the end of the module, you’ll be able to recognise when atomic accesses are required, understand how AXI supports them, and appreciate the design decisions behind each mechanism.

Transfer Behavior and Transaction Ordering

Welcome to this module on Atomic Accesses in the AXI protocol. In modern systems, multiple agents often need to access shared resources at the same time. In these situations, it’s not enough for transactions to be fast — they also need to be atomic, ensuring that critical read-modify-write sequences complete without interference. In this module, we’ll explore what atomic accesses are and why they are used. We’ll then look in detail at the two mechanisms AXI provides to support atomicity: locked accesses and exclusive accesses. You’ll see how each approach works, how they differ, and the trade-offs involved in their use. In particular, we’ll focus on how locked and exclusive accesses affect interconnect behaviour and bandwidth utilisation, and why exclusive accesses are generally preferred in high-performance systems. By the end of the module, you’ll be able to recognise when atomic accesses are required, understand how AXI supports them, and appreciate the design decisions behind each mechanism.

AXI Update - Issue F

Welcome to this module on AXI Issue F updates. As AXI has evolved, new features have been added to address emerging system requirements, particularly around coherency, performance optimisation, and tighter integration with cache-based architectures. Issue F introduces a number of these updates, extending AXI beyond its original transaction model.In this module, we’ll explore the key additions introduced in Issue F, including atomic transactions, cache stashing, and several new transaction types and signalling mechanisms. We’ll also look at updates related to coherency signalling, data integrity, and address translation.Rather than focusing on implementation detail, the emphasis here is on understanding what these features are, why they were introduced, and how they extend existing AXI behaviour.By the end of the module, you’ll have a clear view of the most important Issue F updates and how they fit into the ongoing evolution of the AXI protocol.

AXI Update - Issue G

This module introduces the key enhancements added to the AXI protocol in Release G. These updates focus on improving read behaviour, supporting system-level resource control, and extending cache management capabilities. Learners will explore new read data handling features, including read data chunking and changes to read interleaving behaviour. The module also introduces Memory Partitioning and Monitoring (MPAM), which enables finer control over shared system resources. Finally, the module examines updates related to cache management operations on write transactions, including persistence behaviour. By the end of this module, learners will understand how the Release G updates extend AXI functionality to better support performance optimisation, resource management, and cache-aware system design.

AXI Update - Issue H

This module introduces the enhancements added to the AXI protocol in Issue H, with a particular focus on memory safety, transaction flexibility, and extended write behaviours. Learners will explore updates to regular and untranslated transactions, before diving into memory tagging, including its purpose, signalling, and read and write operation behaviour. The module also introduces several new transaction types, such as prefetch transactions, write plus cache management operations, and write zero transactions. By the end of this module, learners will understand how Issue H extends AXI to better support modern system requirements such as memory protection, performance optimisation, and improved data handling.

ACE Lite (optional)

ACE-Lite is included as an optional module for learners who may encounter it in existing systems or legacy designs. While ACE-Lite introduced coherency-related concepts to AXI-based systems, it is no longer treated as a separate focus in modern AMBA specifications and has been absorbed into the wider AXI and ACE landscape. New designs typically target more recent AMBA features, so this module is provided for background and context rather than as essential knowledge. Welcome to this module on ACE-Lite. Up to this point in the course, we’ve focused on AXI as a high-performance, non-coherent interface. In many systems, however, components need to share data while maintaining a consistent view of memory. This is where coherency becomes important.In this module, we’ll first revisit the limits of non-coherent AXI-based systems and explore why coherency is required. We’ll then look at common coherency solutions at a high level, before introducing ACE-Lite and the problem it was designed to solve.Although ACE-Lite was originally defined as a separate protocol, it has since been absorbed into later versions of AXI. We treat it separately here to clearly highlight the additional concepts it introduces and how they extend standard AXI behaviour. By the end of this module, you’ll understand what ACE-Lite is, when it is used, and how it enables limited coherency while preserving the performance characteristics of AXI. Please note this is an optional module - ACE Lite used to be a separate protocol but was folded into AMBA AXI version 5.