Explore how High-Level Synthesis (HLS) enables the development of optimized machine learning accelerators for ASIC and FPGA implementations in this technical talk by Siemens EDA Technical Director Russell Klein. Learn to balance communication, computation, and data movement while evaluating multiple accelerator architectures within larger systems. Discover techniques for using HLS to rapidly generate and assess RTL implementations from algorithmic descriptions, determine optimal quantization for features and weights at both layer and network levels, and investigate caching strategies' effects on power and performance. Gain valuable insights into deploying machine learning solutions in resource-constrained Edge and IoT systems through the strategic application of High-Level Synthesis.