Adjusting Network-on-Chip Topologies for Design Goals and Architectures

Explore the innovative Sparse Hamming Graph topology for Network-on-Chip (NoC) design in this conference talk from the 60th Design Automation Conference. Dive into the challenges of designing scalable NoCs for chips with hundreds to thousands of cores. Discover four key design principles for NoC topologies and learn how the Sparse Hamming Graph offers an adjustable cost-performance trade-off. Examine the custom toolchain developed for efficient topology customization, leveraging approximate floorplanning and link routing for accurate predictions. Compare the performance of this novel approach against established topologies and understand how it addresses diverse design goals for different chips. Gain insights into the future of chip design and network architecture through this comprehensive presentation by Patrick Iff from the Scalable Parallel Computing Lab at ETH Zurich.